SH7205 Datasheet, PDF (340/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
CKIO
A25 to A0
CSn
RD_WR
RD
WEn
D31 to D0
DACTn
Ts Tw1 ^...
... _{Twn Tend Tdw1 Tdwn Tpw1 Tpw2} ... _{Tend Tdw1 Tdwn}
Tn1 Tnm
Bus access (first time)
Write cycle wait
A0
CS assert wait
Bus access
(second and subsequent times)
Page write
cycle wait
A1
CS delay cycle
during write (end only)
WR assert wait
Write data
output wait
WR assert wait
Write data output Write data
delay cycle _{output wait}
D0
Write data output
delay cycle
D1
Figure 10.5 Basic Bus Timing (Page Write Operation in Byte-Write Strobe Mode)
1. Ts (Internal Bus Access Start)
This is a bus access request cycle initiated by the internal bus master to the external bus as the
target. CSn is always high during this cycle. In the next cycle, A25 to A0, BCn, and the write
data change.
2. Tw1 to Twn (Read Cycle Wait, Write Cycle Wait)
For the first bus access in a page access, the control of the wait operation from internal bus
access start to the wait end cycle is the same as in normal access.
Rev. 1.00 Mar. 25, 2008 Page 308 of 1868
REJ09B0372-0100