SH7205 Datasheet, PDF (1337/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 25 AT Attachment Packet Interface (ATAPI)
Initial
Bit
Bit Name Value R/W Description
9
DTCD
0
R/W This bit controls operating mode for device
terminations that occur continuously during ultra DMA.
No abnormal termination occurs if the specified
number of transfers has not been reached after device
termination acceptance. Transfer will restart at a
DMARQ from the next device.
Some of the existing ATA devices handle device
terminations in the same way as pauses. Therefore, if
the specified number of transfers has not been
reached after device termination acceptance, no
abnormal termination occurs, and it is necessary to
restart transfer at a DMARQ from the next device. This
operating mode is called “device termination
continuation mode.”
1: Device termination continuation mode prohibited
0: Device termination continuation mode
8


R
Reserved
7
RESET
0
R/W This bit controls resetting the ATAPI device. Setting
the bit to 1 causes the ATAPI reset signal to be
asserted. The IDERST# signal is an active-low signal.
If the bit is set to 1, the IDERST# signal goes low. If
the bit is cleared to 0, the IDERST# signal goes high.
6
M/S
0
R/W This bit selects an ATAPI device as master or slave.
1: The ATAPI device is selected as master.
0: The ATAPI device is selected as slave.
5

1
R
Reserved
The write value should always be 1.
4
UDMAEN 0
R/W This bit is an ultra DMA enable bit.
To use ultra DMA mode, set the bit to 1. To use
multiword DMA or PIO mode, clear the bit to 0.
3

0
R
Reserved
Rev. 1.00 Mar. 25, 2008 Page 1305 of 1868
REJ09B0372-0100