SH7205 Datasheet, PDF (1212/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
24.3.19 Interrupt Status Register 0 (INTSTS0)
INTSTS0 indicates the statuses of various interrupts.
This register is initialized by a power-on reset. The DVST and DVSQ[2:0] bits are initialized by a
USB bus reset.
Bit: 15 14 13 12 11 10 9
8
7
VBINT RESM SOFR DVST CTRT BEMP NRDY BRDY VBSTS
Initial value: 0
0
0
*¹
0
0
0
0
-
R/W: R/W*² R/W*² R/W*² R/W*² R/W*² R
R
R
R
6
5
4
DVSQ[2:0]
*¹
*¹
*¹
R
R
R
3
2
1
0
VALID
CTSQ[2:0]
0
0
0
0
R/W*² R
R
R
Initial
Bit
Bit Name
Value R/W Description
15
VBINT
0
R/W*² VBUS Transition Detection Interrupt Status*³*⁴
This bit is set to 1 on detecting a transition of the
VBUS pin input. When a VBINT interrupt has
occurred, read the VBSTS bit, which monitors the
VBUS pin level, several times and confirm that the
same value is read consecutively in order to prevent
chattering.
0: VBUS interrupt has not occurred
1: VBUS interrupt has occurred
14
RESM
0
R/W*² Resume Interrupt Status*³*⁴*⁵
When the function controller function is selected, this
bit is set to 1 on detecting the falling edge of the
signal on the DP pin in the suspended state (DVSQ
= 1xx).
0: Resume interrupt has not occurred
1: Resume interrupt has occurred
Rev. 1.00 Mar. 25, 2008 Page 1180 of 1868
REJ09B0372-0100