SH7205 Datasheet, PDF (466/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
Note: If registers are not reloaded, set ECLR = 1 so that the DEN bit is cleared.
11.5.2 DMA Interrupt Requests
The DMAC provides two types of interrupt request signals for the interrupt controller: interrupt
request signals per channel (DMINTn_N, n = 0 to 13) and a common interrupt request signal
(DMINTA_N) that is a collection of interrupt requests per channel.
Figure 11.5 is a block diagram of generating interrupt request signals per channel and a common
interrupt request signal.
If the DMA interrupt control bit (DINTM) of the channel corresponding to the DMA interrupt
control register (DMICNT) is set to 1 when a DMA transfer ends, an interrupt request for the
corresponding channel is generated.
Only those channels for which the DMA common interrupt request signal control bit (DINTA) of
the DMA common interrupt control register (DMICNTA) is set to 1 are collected into one and
output as the common interrupt request signal.
The generated interrupt request can be cleared to 0 by writing 1 to the DMA transfer end condition
detect bit (DEDET) of the corresponding channel.
Rev. 1.00 Mar. 25, 2008 Page 434 of 1868
REJ09B0372-0100