SH7205 Datasheet, PDF (1541/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 28 I/O Ports
28.2.1 Port A Data Register L (PADRL)
PADRL is a 16-bit readable/writable register that stores port A data. The PA15DR to PA0DR bits
correspond to the PA15 to PA0 pins, respectively.
When a pin function is general output, if a value is written to PADRL, that value is output from
the pin, and if PADRL is read, the register value is returned regardless of the pin state.
When a pin function is general input, if PADRL is read, the pin state, not the register value, is
returned directly. If a value is written to PADRL, although that value is written into PADRL, it
does not affect the pin state. Table 28.2 summarizes PADRL read/write operations.
Bit: 15
PA15
DR
Initial value: 0
R/W: R/W
14
PA14
DR
0
R/W
13
PA13
DR
0
R/W
12
PA12
DR
0
R/W
11
PA11
DR
0
R/W
10
PA10
DR
0
R/W
9
PA9
DR
0
R/W
8
PA8
DR
0
R/W
7
PA7
DR
0
R/W
6
PA6
DR
0
R/W
5
PA5
DR
0
R/W
4
PA4
DR
0
R/W
3
PA3
DR
0
R/W
2
PA2
DR
0
R/W
1
PA1
DR
0
R/W
0
PA0
DR
0
R/W
Initial
Bit
Bit Name Value
R/W Description
15
PA15DR 0
R/W See table 28.2.
14
PA14DR 0
R/W
13
PA13DR 0
R/W
12
PA12DR 0
R/W
11
PA11DR 0
R/W
10
PA10DR 0
R/W
9
PA9DR 0
R/W
8
PA8DR 0
R/W
7
PA7DR 0
R/W
6
PA6DR 0
R/W
5
PA5DR 0
R/W
4
PA4DR 0
R/W
3
PA3DR 0
R/W
2
PA2DR 0
R/W
1
PA1DR 0
R/W
0
PA0DR 0
R/W
Rev. 1.00 Mar. 25, 2008 Page 1509 of 1868
REJ09B0372-0100