SH7205 Datasheet, PDF (1509/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 27 Pin Function Controller (PFC)
Table 27.4 Multiplexed Pins (Port D)
0000
Setting Function 1
Register (General I/O)
PDCRL1 PD2 I/O (port)
PD1 I/O (port)
PD0 /O (port)
Setting of Mode Bits (PDnMD[3:0])
0001
0010
0011
0100
Function 2
(Related Module)
Function 3
(Related Module)
Function 4
(Related Module)
Function 5
(Related Module)
TEND0 output
(DMAC)
A23 output (address) SCK2 I/O (SCIF)
IRQ6 input (INTC)
DACK0 output
(DMAC)
A24 output (address) DACT0 output
(DMAC)
IRQ5 input (INTC)
DREQ0 input
(DMAC)
A25 output (address) ADTRG input (ADC) IRQ4 input (INTC)
Table 27.5 Multiplexed Pins (Port E)
0000
Setting Function 1
Register (General I/O)
PECRL4 PE13 I/O (port)
PE12 input (port)
PECRL3 PE11 I/O (port)
PE10 input (port)
PE9 I/O (port)
PE8 input (port)
PECRL2 PE7 I/O (port)
Setting of Mode Bits (PEnMD[3:0])
0001
0010
0011
Function 2
(Related Module)
Function 3
(Related Module)
Function 4
(Related Module)
TxD4 output (SCIF) SDA2 I/O (IIC3)

RxD4 input (SCIF) SCL2 I/O (IIC3)

TxD3 output (SCIF) SDA1 I/O (IIC3)

RxD3 input (SCIF) SCL1 I/O (IIC3)

TxD2 output (SCIF) SDA0 I/O (IIC3)

RxD2 input (SCIF) SCL0 I/O (IIC3)

SCK1 I/O (SCIF)
SCS1 I/O (SSU)

PE6 I/O (port)
PE5 I/O (port)
PE4 I/O (port)
PECRL1 PE3 I/O (port)
PE2 I/O (port)
PE1 I/O (port)
PE0 I/O (port)
TxD1 output (SCIF) SSO1 I/O (SSU)

RxD1 input (SCIF) SSI1 I/O (SSU)

SCK0 I/O (SCIF)
SSCK1 I/O (SSU) 
RTS0 I/O (SCIF)
SCS0 I/O (SSU)

CTS0 I/O (SCIF)
SSO0 I/O (SSU)

TxD0 output (SCIF) SSI0 I/O (SSU)

RxD0 input (SCIF) SSCK0 I/O (SSU) 
0100
Function 5
(Related Module)






SSIDATA5 output
(SSIF)
SSIWS5 I/O (SSIF)
SSISCK5 I/O (SSIF)

TIOC2B I/O (MTU2)
TIOC2A I/O (MTU2)


Rev. 1.00 Mar. 25, 2008 Page 1477 of 1868
REJ09B0372-0100