SH7205 Datasheet, PDF (140/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 4 Multi-Core Processor
4.2.2 Semaphore Registers 0 to 31 (SEMR0 to SEMR31)
Semaphore registers 0 to 31 (SEMR0 to SEMR31) support exclusive control for resource access
by the two CPUs.
Access to SEMR0 to SEMR31 by a given CPU does not interfere with the operation of the other
CPU or the DMAC.
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
-
-
- SEMF
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R R/W
Bit
7 to 1
0
Bit Name

Initial
Value
All 0
SEMF
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 1.
R/W Used to support exclusive control for the two CPUs.
The value written to this bit is retained.
If this bit is read, the value of this bit is read out to the
CPU and this bit is cleared automatically.
Rev. 1.00 Mar. 25, 2008 Page 108 of 1868
REJ09B0372-0100