SH7205 Datasheet, PDF (470/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
(2) DMA End Output Signal (TENDi, i = 0 to 3)
If DMA transfer by the DREQi request from an external pin is selected, the read or write
destination is normal space (CS0 to CS5), and transfer mode is cycle-stealing transfer mode, the
DMA end output signal (TENDi) can be output to outside the LSI. For access to LSI interior or
SDRAM space or when transfer mode is pipelined transfer mode, the TENDi signal is not output.
• To read from normal space by DMA, set the DMA end signal output control bits (DTCM) of
the DMA mode register (DMMODn) to select that an end signal is output in the last read cycle
(DTCM = 01). TENDi is output when the last one data unit is read by DMA. The TENDi
output timing is the same as the DMA-active signal (DACTi) timing (see section 11.9, DMA
Acknowledge Signal Output and DMA-Active Signal Output, and section 10, Bus State
Controller (BSC)). If DTCM is set to other than 01, TENDi is not output.
• To write to normal space by DMA, set the DTCM bits of DMMODn to select that an end
signal is output in the last write cycle (DTCM = 10). TENDi is output when the last one data
unit is written by DMA. The TENDi output timing is the same as the DMA-active signal
(DACTi) timing (see section 11.9, DMA Acknowledge Signal Output and DMA-Active Signal
Output, and section 10, Bus State Controller (BSC)). If DTCM is set to other than 10, TENDi
is not output.
Rev. 1.00 Mar. 25, 2008 Page 438 of 1868
REJ09B0372-0100