SH7205 Datasheet, PDF (1208/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name Value
R/W Description
5
PIPE5NRDYE 0
R/W NRDY Interrupt Enable for PIPE5
Enables/disables the interrupt request when PIPE5
NRDY interrupt is detected.
0: Interrupt output disabled
1: Interrupt output enabled
4
PIPE4NRDYE 0
R/W NRDY Interrupt Enable for PIPE4
Enables/disables the interrupt request when PIPE4
NRDY interrupt is detected.
0: Interrupt output disabled
1: Interrupt output enabled
3
PIPE3NRDYE 0
R/W NRDY Interrupt Enable for PIPE3
Enables/disables the interrupt request when PIPE3
NRDY interrupt is detected.
0: Interrupt output disabled
1: Interrupt output enabled
2
PIPE2NRDYE 0
R/W NRDY Interrupt Enable for PIPE2
Enables/disables the interrupt request when PIPE2
NRDY interrupt is detected.
0: Interrupt output disabled
1: Interrupt output enabled
1
PIPE1NRDYE 0
R/W NRDY Interrupt Enable for PIPE1
Enables/disables the interrupt request when PIPE1
NRDY interrupt is detected.
0: Interrupt output disabled
1: Interrupt output enabled
0
PIPE0NRDYE 0
R/W NRDY Interrupt Enable for PIPE0
Enables/disables the interrupt request when PIPE0
NRDY interrupt is detected.
0: Interrupt output disabled
1: Interrupt output enabled
Rev. 1.00 Mar. 25, 2008 Page 1176 of 1868
REJ09B0372-0100