SH7205 Datasheet, PDF (317/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
In addition to the restrictions for disabled page access, the following restrictions are
required.
CSON ≤ min. (CSPRWAIT, CSPWWAIT)
WRON ≤ CSPWWAIT, RDON ≤ CSPRWAIT
WDON ≤ CSPWWAIT
10.4.7 SDRAM Refresh Control Register 0 (SDRFCNT0)
SDRFCNT0 controls self-refresh operation.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- DSFEN
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W
Bit
Bit Name
31 to 1 
0
DSFEN
Initial
Value
All 0
0
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
SDRAM Common Self-Refresh Operation Enable
This bit controls self-refresh operation for all channels
simultaneously. Setting DSFEN to 1 performs auto-refresh
cycle operation, immediately after which self-refresh
operation begins. Clearing DSFEN to 0 ends self-refresh
operation, and auto-refresh operation resumes
immediately afterward. The value written to this bit is
reflected when self-refresh operation starts, if DSFEN was
set to 1, or when auto-refresh operation starts following
the end of self-refresh operation, if DSFEN was cleared to
0.
0: Self-refresh disabled
1: Self-refresh enabled
Rev. 1.00 Mar. 25, 2008 Page 285 of 1868
REJ09B0372-0100