SH7205 Datasheet, PDF (1755/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 32 List of Registers
Module
Name
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
RCAN-TL1 MBn_LAFM0_0 
(n = 0 to 31)
STDID_LAFM[3:0]
STDID_LAFM[10:4]

IDE
EXTID_LAFM[17:16]
MBn_LAFM0_0 IDE

(n = 0 to 31)

STDID_LAFM[5:0]
STDID_LAFM[10:6]
EXTID_LAFM[17:16]
MBn_LAFM1_0
(n = 0 to 31)
EXTID_LAFM[15:8]
EXTID_LAFM[7:0]
MBn_DATA_01_
0 (n = 0 to 31)
MSG_DATA_0
MSG_DATA_1
MBn_DATA_23_
0 (n = 0 to 31)
MSG_DATA_2
MSG_DATA_3
MBn_DATA_45_
0 (n = 0 to 31)
MSG_DATA_4
MSG_DATA_5
MBn_DATA_67_
0 (n = 0 to 31)
MSG_DATA_6
MSG_DATA_7
MBn_CONTROL 

NMC


1_0 (n = 0)




MBC[2:0]
DLD[3:0]
MBn_CONTROL 

NMC
ATX
DART
1_0 (n = 0 to 31)




MBC[2:0]
DLC[3:0]
MBn_TIMES
TS15
TS14
TS13
TS12
TS11
TS10
TS9
TS8
TAMP_0 (n = 0
TS7
TS6
TS5
TS4
TS3
TS2
TS1
TS0
to 15, 30, 31)
MBn_TTT_0
(n = 24 to 30)
TTT15
TTT7
TTT14
TTT6
TTT13
TTT5
TTT12
TTT4
TTT11
TTT3
TTT10
TTT2
TTT9
TTT1
TTT8
TTT0
MBn_TTCON
TTW[1:0]
Offset[5:0]
TROL_0





(n = 24 to 29)
rep_factor[2:0]
MCR_1
MCR15
MCR14



TST[2:0]
MCR7
MCR6
MCR5


MCR2
MCR1
MCR0
Rev. 1.00 Mar. 25, 2008 Page 1723 of 1868
REJ09B0372-0100