SH7205 Datasheet, PDF (1440/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
GR_SABSET
GR_DCSET
SB_STEN
SA_STEN
DMA
transfer
DMA3
DMA4
DMA2
1...N1
Operation with 2 inputs (SA and SB)
SA, SB = Nx, DC = Lx
Operation with 1 input (SB)
SA = invalid, SB = My, DC = Ly
1...N1
Completion of the
DMA3 transfer
...Nx ^{Completion of the}
DMA4 transfer
...Nx
Completion of the
DMA2 transfer
...Nx
1...M1
...My
1...L1 ...Lx
1...L1
DMA4 request
DMA3 request
DMA2 request
SBHF_STAT(0)
SBHF_STAT(1)
SAHF_STAT(0)
SAHF_STAT(1)
DCHF_STAT(0)
DCHF_STAT(1)
INT_SHFUL (SB buffer full)
INT_ASHFUL (SA buffer full)
INT_DHFUL (DC buffer full)
INT_GR
BLT interrupt
Issue of Issue of Issue of
INTDIS INTDIS INTDIS
Issue of
INTDIS
Figure 26.19 Summary of Operations between Blitter and External Memory
Rev. 1.00 Mar. 25, 2008 Page 1408 of 1868
REJ09B0372-0100