SH7205 Datasheet, PDF (883/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 18 I²C Bus Interface 3 (IIC3)
Bit
2 to 0
Bit Name
BC[2:0]
Initial
Value
000
R/W Description
R/W Bit Counter
These bits specify the number of bits to be transferred
next. When read, the remaining number of transfer bits
is indicated. With the I²C bus format, the data is
transferred with one addition acknowledge bit. Should
be made between transfer frames. If these bits are set
to a value other than B'000, the setting should be made
while the SCL pin is low. The bit value returns to B'000
automatically at the end of a data transfer including the
acknowledge bit. And the value becomes B'111
automatically after the stop condition detection. These
bits are cleared by a power-on reset and in software
standby mode and module standby mode. These bits
are also cleared by setting the IICRST bit of ICCR2 to
1. With the clocked synchronous serial format, these
bits should not be modified.
I²C Bus Format Clocked Synchronous Serial Format
000: 9 bits
000: 8 bits
001: 2 bits
001: 1 bit
010: 3 bits
010: 2 bits
011: 4 bits
011: 3 bits
100: 5 bits
100: 4 bits
101: 6 bits
101: 5 bits
110: 7 bits
110: 6 bits
111: 8 bits
111: 7 bits
Rev. 1.00 Mar. 25, 2008 Page 851 of 1868
REJ09B0372-0100