SH7205 Datasheet, PDF (1413/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
26.3.25 Panel-Output Horizontal Timing Setting Register for Output-Block
(MGR_MIXHTMG)
The register MGR_MIXHTMG sets the timing of signal output to the panel in the horizontal
direction. The register value is applied in synchronization with the VSYNC signal. For details, see
section 26.4.1 (5), Setting of Panel Output.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
WPH
Initial value: -
-
-
-
-
-
-
-
-
-
0
0
0
1
0
1
R/W: R
R
R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
PDPH
Initial value: -
-
-
-
-
-
-
0
0
0
0
0
1
1
1
1
R/W: R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit name
31 to 22 
21 to 16 WPH
15 to 9 
8 to 0 PDPH
Initial
Value
R/W
Undefined R
H'05
R/W
Undefined R
H'00F
R/W
Description
Reserved
The read value is undefined. The write value should
always be 0.
Panel Output HSYNC Pulse Width
These bits set the HSYNC pulse width for panel
output using the number of DCLKIN from the falling
edge of HSync_out.
Valid range: 1 to 63 pixels
Reserved
The read value is undefined. The write value should
always be 0.
Panel Output Image Horizontal Reading Start Timing
These bits set the start timing to read image to be
output to the panel in the horizontal direction using
the number of DCLKIN from WPH.
Valid range: 0 to 511 pixels
Rev. 1.00 Mar. 25, 2008 Page 1381 of 1868
REJ09B0372-0100