SH7205 Datasheet, PDF (261/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 User Break Controller (UBC)
8.3.5 Break Bus Cycle Register (BBR)
BBR is a 16-bit readable/writable register, which specifies (1) disabling or enabling of user break
interrupts, (2) including or excluding of the data bus value, (3) C bus cycle or I bus cycle, (4)
instruction fetch or data access, (5) read or write, and (6) operand size as the break conditions.
Bit: 15 14 13 12 11 10
-
- UBID DBE
-
-
Initial value: 0
0
0
0
0
0
R/W: R R R/W R/W R R
9
8
7
6
5
4
3
2
1
0
-
CP
CD[1:0]
ID[1:0]
RW[1:0]
SZ[1:0]
0
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
15, 14
Bit Name

13
UBID
12
DBE
11 to 9 
8
CP
Initial
Value
All 0
0
0
All 0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W User Break Interrupt Disable
Disables or enables user break interrupt requests when
a break condition is satisfied.
0: User break interrupt requests enabled
1: User break interrupt requests disabled
R/W Data Break Enable
Selects whether the data bus condition is included in
the break conditions.
0: Data bus condition is not included in break
conditions.
1: Data bus condition is included in break conditions.
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W I Bus Select
Select permission or prohibition when the bus cycle of
the break condition is the I bus cycle. However, when
the C bus cycle is selected, this bit is invalidated (only
the CPU cycle).
0: The condition of the I bus cycle is not compared.
1: The condition of the I bus cycle is compared.
Rev. 1.00 Mar. 25, 2008 Page 229 of 1868
REJ09B0372-0100