SH7205 Datasheet, PDF (921/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 19 Serial Sound Interface with FIFO (SSIF)
19.3.1 Control Register (SSICR)
SSICR is a readable/writable 32-bit register that controls the IRQ, selects the polarity status, and
sets operating mode.
Bit: 31 30 29
CKS[1:0]
-
Initial value: 0
0
0
R/W: R/W R/W R
28 27 26 25 24 23 22 21 20 19 18 17 16
-
UIEN OIEN IIEN
-
CHNL[1:0]
DWL[2:0]
SWL[2:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SCKD SWSD SCKP SWSP SPDP SDTA PDTA DEL
CKDV[3:0]
MUEN - TRMD EN
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W
Bit
31, 30
29, 28
27
26
Initial
Bit Name Value R/W Description
CKS[1:0] 00
R/W Oversampling Clock Select
These bits select the clock source for oversampling.
CKS[1:0]
Clock Operating Mode
Setting 0 or 1
2
3
00
AUDIO_X1 input
01
AUDIO_CLK input*
10
EXTAL
CKIO
Setting
input
input
prohibited
11
Setting prohibited
Note: * When using AUDIO_CLK, set the PH15MD0
bit in port control register L4 (PHCRL4) to 1.
—
All 0 R
Reserved
The read value is undefined. The write value should
always be 0.
UIEN
0
R/W Underflow Interrupt Enable
0: Underflow interrupt is disabled.
1: Underflow Interrupt is enabled.
OIEN
0
R/W Overflow Interrupt Enable
0: Overflow interrupt is disabled.
1: Overflow interrupt is enabled.
Rev. 1.00 Mar. 25, 2008 Page 889 of 1868
REJ09B0372-0100