SH7205 Datasheet, PDF (912/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 18 I²C Bus Interface 3 (IIC3)
(a) SCL is normally driven
Synchronous clock ^*1
SCL pin
Internal SCL monitor
V_IH
Internal^*2
delay
The monitor value is
high level.
Time for
monitoring SCL
(b) When SCL is driven to low by the slave device
Synchronous clock *¹
SCL is driven to low by
the slave device.
SCL pin
Internal SCL monitor
V_IH
Internal ^*2
delay
SCL is not driven to low.
V_IH
*²
Internal
delay
Time for
The monitor value
The monitor value
is high level.
is low level.
Time for
monitoring SCL
monitoring SCL
The monitor value
is high level.
Time for
monitoring SCL
(c) When the rising speed of SCL is lowered
Synchronous clock ^*1
SCL pin
Internal SCL monitor
V_IH
SCL is not driven to low.
Internal ^*2
delay
The monitor value is low level.
SCL
Notes: 1. The clock is the transfer rate clock set by the CKS[3:0] bits in the I²C bus control register 1 (ICCR1).
2. When the NF2CYC bit in NF2CYC (NF2CYC) is set to 0, the internal delay time is 3 to 4 t_pcyc.
When this bit is set to 1, the internal delay time is 4 to 5 t_pcyc.
Figure 18.22 Bit Synchronous Circuit Timing
The frequency is not
the setting frequency.
Rev. 1.00 Mar. 25, 2008 Page 880 of 1868
REJ09B0372-0100