SH7205 Datasheet, PDF (815/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Error handling
No
ORER = 1?
Yes
Overrun error handling
No
ER = 1?
Yes
Receive error handling
No
BRK = 1?
Yes
Break handling
• Whether a framing error or parity error
has occurred in the receive data that
is to be read from the receive FIFO
data register (SCFRDR) can be
ascertained from the FER and PER
bits in the serial status register
(SCFSR).
• When a break signal is received,
receive data is not transferred to
SCFRDR while the BRK flag is set.
However, note that the last data in
SCFRDR is H'00, and the break data
in which a framing error occurred is
stored.
No
DR = 1?
Yes
Read receive data in SCFRDR
Clear DR, ER, BRK flags
in SCFSR,
and ORER flag in SCLSR to 0
End
Figure 16.8 Sample Flowchart for Receiving Serial Data (cont)
Rev. 1.00 Mar. 25, 2008 Page 783 of 1868
REJ09B0372-0100