SH7205 Datasheet, PDF (1587/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 30 Power-Down Modes
Set SYSCR2 using the program that is placed in a space other than the high-speed on-chip RAM
space. Furthermore, an instruction to read SYSCR2 should be located immediately after the
instruction to write to SYSCR2. Otherwise, normal access to the high-speed on-chip RAM is not
guaranteed.
Note: When writing to this register, see section 30.4, Usage Notes.
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
RAM RAM RAM RAM
WE3 WE2 WE1 WE0
Initial value: 1
1
1
1
1
1
1
1
R/W: R R R R R/W R/W R/W R/W
Initial
Bit Bit Name Value R/W Description
7 to 4 
All 1 R
Reserved
These bits are always read as 1. The write value should
always be 1.
3
RAMWE3 1
R/W RAM Write Enable 3 (page 3 of high-speed on-chip RAM0*)
0: Write to page 3 is disabled
1: Write to page 3 is enabled
2
RAMWE2 1
R/W RAM Write Enable 2 (page 2 of high-speed on-chip RAM0*)
0: Write to page 2 is disabled
1: Write to page 2 is enabled
1
RAMWE1 1
R/W RAM Write Enable 1 (page 1 of high-speed on-chip RAM0*)
0: Write to page 1 is disabled
1: Write to page 1 is enabled
0
RAMWE0 1
R/W RAM Write Enable 0 (page 0 of high-speed on-chip RAM0*)
0: Write to page 0 is disabled
1: Write to page 0 is enabled
Note: * For the addresses of each page, see section 29, On-Chip RAM.
Rev. 1.00 Mar. 25, 2008 Page 1555 of 1868
REJ09B0372-0100