SH7205 Datasheet, PDF (247/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Interrupt Controller (INTC)
7.8 Register Banks
This LSI has 15 register banks used to perform register saving and restoration at high speed for the
interrupt processing. Figure 7.10 shows the register bank configuration.
Registers
General
registers
Control
registers
System
registers
R0
R1
:
:
R14
R15
SR
GBR
VBR
TBR
MACH
MACL
PR
PC
Register banks
R0
R1
Interrupt generated
:
(save)
:
R14
Bank 0
Bank 1
....
Bank 14
GBR
RESBANK
instruction
(restore)
MACH
MACL
PR
IVO
Bank control registers (interrupt controller)
Bank control register
Bank number register
IBCR
IBNR
Note:
: Banked register
IVO: Interrupt vector offset
Figure 7.10 Overview of Register Bank Configuration
Rev. 1.00 Mar. 25, 2008 Page 215 of 1868
REJ09B0372-0100