SH7205 Datasheet, PDF (358/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
CKIO
Multiple reads
SDRAM command
ACT RD DSL RD DSL RD DSL RD PRA
Data bus
d0
d1
d2
d3
ACT: Row and bank activation command
RD: Read command
PRA: Precharge-all-banks command
DSL: Deselect command
Figure 10.17 Multiple Read Timing Example
(Multiple Reads of 4 Data Units, Shortest Timing Settings)
Non-Consecutive Read Commands Issued
CKIO
Multiple writes
SDRAM command
ACT WR DSL WR DSL WR DSL WR PRA
Data bus
d0
d1
d2
d3
ACT: Row and bank activation command
WR: Write command
PRA: Precharge-all-banks command
DSL: Deselect command
Figure 10.18 Multiple Write Timing Example
(Multiple Writes of 4 Data Units, Shortest Timing Settings)
Non-Consecutive Write Commands Issued
Rev. 1.00 Mar. 25, 2008 Page 326 of 1868
REJ09B0372-0100