SH7205 Datasheet, PDF (292/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Cache
(1) Data Array Read
The data specified by the L bit in the address is read from the entry address specified by the
address and the entry corresponding to the way.
(2) Data Array Write
The longword data specified by the data is written to the position specified by the L bit in the
address from the entry address specified by the address and the entry corresponding to the way.
1. Instruction cache
1.1 Address array access
(a) Address specification
Read access
31
23 22
13 12 11 10
43210
111100000 *----------* W
Entry address 0 * 0 0
Write access
31
23 22
13 12 11 10
43210
111100000 *----------* W
Entry address A * 0 0
(b) Data specification (both read and write accesses)
31 29 28
11 10 9
43210
0 0 0 Tag address (28 to 11) E
LRU
XXXV
2. Operand cache
2.1 Address array access
(a) Address specification
Read access
31
23 22
13 12 11 10
43210
111100001 *----------* W Entry address 0 * 0 0
Write access
31
23 22
13 12 11 10
43210
111100001 *----------* W Entry address A * 0 0
(b) Data specification (both read and write accesses)
31 29 28
11 10 9
43210
0 0 0 Tag address (28 to 11) E
LRU
X X UV
1.2 Data array access (both read and write accesses)
(a) Address specification
31
23 22
13 12 11 10
43210
111100010 *----------* W
Entry address
L 00
(b) Data specification
31
0
Longword data
2.2 Data array access (both read and write accesses)
(a) Address specification
31
23 22
13 12 11 10
43210
111100011 *----------* W Entry address
L 00
(b) Data specification
31
0
Longword data
[Legend]
*: Don't care
E: Bit 10 of entry address for read, don't care for write
X: 0 for read, don't care for write
Figure 9.4 Specifying Address and Data for Memory-Allocated Cache Access
Rev. 1.00 Mar. 25, 2008 Page 260 of 1868
REJ09B0372-0100