SH7205 Datasheet, PDF (1025/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 20 Controller Area Network (RCAN-TL1)
(4) Timer Status Register (TSR)
This register is a 16-bit read-only register, and allows the CPU to monitor the Timer Compare
Match status and the Timer Overrun Status.
• TSR (Address = H'088)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
TSR4 TSR3 TSR2 TSR1 TSR0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bits 15 to 5: Reserved. The written value should always be ‘0’ and the returned value is ‘0’.
Bit 4 to 0 — RCAN-TL1 Timer Status (TSR[4:0]): This read-only field allows the CPU to
monitor the status of the Cycle Counter, the Timer and the Compare Match registers. Writing to
this field has no effect.
Bit 4 — Start of New System Matrix (TSR4): Indicates that a new system matrix is starting.
When CCR = 0, this bit is set at the successful completion of reception/transmission of time
reference message.
Bit4: TSR4
0
1
Description
A new system matrix is not starting (initial value)
[Clearing condition] Writing ‘1’ to IRR10 (Cycle Counter Overflow Interrupt)
Cycle counter reached zero
[Setting condition]
When the Cycle Counter value changes from the maximum value (CMAX) to
H'0. Reception/transmission of time reference message is successfully
completed when CMAX!= 3'b111 and CCR = 0
Bit 3 — Timer Compare Match Flag 2 (TSR3): Indicates that a Compare-Match condition
occurred to the Timer Compare Match Register 2 (TCMR2). When the value set in the TCMR2
matches to Cycle Time Register (TCMR2 = CYCTR), this bit is set if TTCR0 bit12 = 1. Please
note that this bit is read-only and is cleared when IRR11 (Timer Compare Match Interrupt 2) is
cleared.
Rev. 1.00 Mar. 25, 2008 Page 993 of 1868
REJ09B0372-0100