SH7205 Datasheet, PDF (1268/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
• When the selected pipe is for isochronous transfer and set in the IN direction:
The IITV bits should be used in combination with IFIS = 1. With IFIS = 0, the module
transmits data packets in response to the received tokens regardless of the IITV bit setting.
When IFIS = 1 is set, the module clears the FIFO buffer if it does not receive any IN token
within the (micro) frames for the interval specified by the IITV bits.
The module also clears the FIFO buffer when it cannot receive normally because a bus error,
such as a CRC error, has occurred in the IN token.
The FIFO buffer is cleared with the timing of receiving an SOF packet. Even if the SOF packet
is corrupted, the FIFO buffer is cleared with the proper timing of SOF reception by the internal
interpolating function.
The clearing conditions for starting the interval timer differ according to the IITV bit setting
(same as the case with the OUT direction).
(a) Power-on reset
(b) When ACLRM = 1 is set
(c) When USB reset is detected
24.3.40 PIPEn Control Registers (PIPEnCTR) (n = 1 to 5)
The PIPEnCTR registers for PIPE1 to PIPE5 are used to confirm the buffer memory status,
change and confirm the data PID sequence bit, determine whether auto response mode is set,
determine whether auto buffer clear mode is set, and set a response PID for the corresponding
pipe. These registers can be set regardless of the pipe selection in PIPESEL.
This register is initialized by a power-on reset. PID[1:0] are initialized by a USB bus reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BSTS
INB
UFM
CSCLR CSSTS
—
AT
REPM
ACLRM SQCLR SQSET SQMON PBUSY
—
—
—
PID[1:0]
Initial value: 0
0
0
0
—0
0
0
0
0
0 ———
0
0
R/W: R
R R/W*² R
R R/W R/W R*¹/ R*¹/ R
R
R
R
R R/W R/W
W*² W*²
Rev. 1.00 Mar. 25, 2008 Page 1236 of 1868
REJ09B0372-0100