SH7205 Datasheet, PDF (1263/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
24.3.39 Pipe Timing Control Register (PIPEPERI)
PIPEPERI is a register that selects whether the buffer is flushed or not when an interval error
occurred during isochronous IN transfer, and sets the interval error detection interval for PIPE1 to
PIPE9.
This register is initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
— IFIS —
—
—
—
—
—
—
—
—
IITV[2:0]
Initial value: -
-
-
0
-
-
-
-
-
-
-
-
-
0
0
0
R/W: R
R
R R/W R
R
R
R
R
R
R
R
R R/W R/W R/W
Bit
Bit Name
15 to 13 
12
IFIS
Initial
Value
R/W
Undefined R
0
R/W
Description
Reserved
Undefined values are read from these bits. The write
value should always be 0.
Isochronous IN Buffer Flush*
When the function controller function is selected
while Isochronous transfer and direction are IN
transfer, this module automatically clears the FIFO
buffer when this module fails to receive the IN token
from the USB host within the interval set by the IITV
bits in terms of (micro) frames.
In double buffer mode (DBLB = 1), this module only
clears the data in the plane used earlier.
This module clears the FIFO buffer on receiving the
SOF packet immediately after the (micro) frame in
which this module has expected to receive the IN
token. Even if the SOF packet is corrupted, this
module also clears the FIFO buffer at the right timing
to receive the SOF packet by using the internal
interpolation.
0: The buffer is not flushed.
1: The buffer is flushed.
Note: When the selected pipe is not for the
isochronous transfer, set this bit to 0.
Rev. 1.00 Mar. 25, 2008 Page 1231 of 1868
REJ09B0372-0100