SH7205 Datasheet, PDF (795/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Table 16.8 Maximum Bit Rates with External Clock Input
(Clock Synchronous Mode, t_Scyc = 12t_pcyc)
Pφ (MHz)
External Input Clock (MHz) Maximum Bit Rate (bits/s)
8
0.6666
666666.6
16
1.3333
1333333.3
24
2.0000
2000000.0
28.7
2.3916
2391666.6
30
2.5000
2500000.0
33
2.7500
2750000.0
16.3.9 FIFO Control Register (SCFCR)
SCFCR resets the quantity of data in the transmit and receive FIFO data registers, sets the trigger
data quantity, and contains an enable bit for loop-back testing. SCFCR can always be read and
written to by the CPU.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
RSTRG[2:0]
RTRG[1:0]
TTRG[1:0]
MCE TFRST RFRST LOOP
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
15 to 11 —
Initial
Value
All 0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Mar. 25, 2008 Page 763 of 1868
REJ09B0372-0100