SH7205 Datasheet, PDF (1370/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
Initial
Bit
Bit name Value
R/W Description
5, 4
SAHF_STAT 00
R
Input Buffer A Half-control of Data Source for the
Blitter
These bits indicate the states of the buffers SA1 (bit
4) and SA2 (bit 5).
00: Both SA1 and SA2 are empty.
01: The size of SA1 coincides but buffer SA2 is
empty.
10: The size of SA2 coincides but buffer SA1 is
empty.
11: The size of both buffers SA1 and SA2 coincide.
3, 2

Undefined R
Reserved
The read value is undefined.
1
SB_REND 0
R
Access Mode of Input Buffer B, Source for the Blitter
This bit indicates the access mode for buffer B.
0: On completion of access for blitting or on standby
mode
1: Access to buffer SB is completed and access to
buffer DC is underway.
0
SA_REND 0
R
Access mode of Input Buffer A, Source for the Blitter
This bit indicates the access mode for buffer A.
0: On completion of access for blitting or on standby
mode
1: Access to buffer SA is completed and access to
buffer DC is underway.
• Each SEHF_STAT bit changes from 0 to 1 when the corresponding buffer SE1 or SE2 is full
or when the amount of pixel data in the SE buffer coincides with the specified number of
pixels.
Furthermore, the SEHF_STAT bit changes from 1 to 0 on completion of reading the data in the
corresponding half of SE buffer (or the data remaining herein).
• Each DCHF_STAT bit changes from 0 to 1 when the corresponding buffer DC1 or DC2 is full
or when the amount of pixel data in the DC buffer coincides with the specified number of
pixels.
Furthermore, the DCHF_STAT bit changes from 1 to 0 on completion of DMA transfer of the
data in the corresponding half of DC buffer (or the data remaining herein).
Rev. 1.00 Mar. 25, 2008 Page 1338 of 1868
REJ09B0372-0100