SH7205 Datasheet, PDF (1284/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Notes: When the function controller function is selected, clear the CSCLR bit to 0.
1. Only 0 can be read.
2. Only 1 can be written to.
3. Modify the ACLRM bit while CSSTS is 0, PID is NAK, and before the CURPIPE bit is
selected. Modify the SQCLR and SQSET bits while CSSTS is 0 and PID is NAK.
Before modifying these bits after modifying the PID bits for the selected pipe from BUF
to NAK, make sure that CSSTS = 0 and PBUSY = 0. However, if the PID bits have
been modified to NAK by this module, checking of PBUSY is not necessary.
Table 24.17 Information Cleared by this Module by Setting ACLRM = 1
Information Cleared by ACLRM Bit
No. Manipulation
Cases in which Clearing the Information
is Necessary
1 All the contents in the FIFO buffer assigned 
to the pertinent pipe
2 When the host controller function is selected, When the interval count value is to be reset
the interval count value when the pertinent
pipe is for interrupt transfer
3 Values of the internal flags related to the
BFRE bit
When the BFRE setting is modified
4 Values of the internal flags related to the
transaction count
When the transaction count function is
forcibly terminated
24.3.42 Transaction Counter Enable Registers (PIPEnTRE) (n = 1 to 5)
The PIPEnTRE registers configure transaction counter operations for PIPE1 to PIPE5. These
registers can be set regardless of the pipe selection in PIPESEL.
This register is initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
— TRENB TRCLR —
—
—
—
—
—
—
—
Initial value: -
-
-
-
-
-
0
0
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R R/W R*¹/ R
R
R
R
R
R
R
R
W*²
Rev. 1.00 Mar. 25, 2008 Page 1252 of 1868
REJ09B0372-0100