SH7205 Datasheet, PDF (1377/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
26.3.5 Interrupt Mask Control Register for Graphics (GR_INTMSK)
The register GR_INTMSK masks 2DG interrupts. When an interrupt event occurs, the interrupt
status register for graphics (GR_IRSTAT) will be set even if the corresponding interrupt is not
enabled (masked). For details on interrupts, see section 26.4.5, Interrupts.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
MSK_ MSK_ MSK_
VSYC UDFL FILD
-
-
-
MSK_
DEMPT
-
MSK_ MSK_ MSK_
ASHFUL DHFUL SHFUL
-
-
-
MSK_
GR
Initial value: -
1
1
1
-
-
-
1
-
1
1
1
-
-
-
1
R/W: R R/W R/W R/W R
R
R R/W R R/W R/W R/W R
R
R R/W
Bit
Bit name
31 to 15 
14
MSK_VSYC
13
MSK_UDFL
Initial
Value
R/W
Undefined R
1
R/W
1
R/W
Description
Reserved
The read value is undefined. The write value should
always be 0.
Output Block VSYNC Input Interrupt Mask
This bit masks a VSYNC input interrupt for the output
block.
0: Enables a VSYNC input interrupt for the output
block.
1: Masks a VSYNC input interrupt for the output
block.
Output Block Output Underflow Interrupt Mask
This bit masks an output underflow interrupt for the
output block.
0: Enables an output underflow interrupt for the
output block.
1: Masks an output underflow interrupt for the output
block.
Rev. 1.00 Mar. 25, 2008 Page 1345 of 1868
REJ09B0372-0100