SH7205 Datasheet, PDF (1584/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 30 Power-Down Modes
30.2.7 Standby Control Register 7 (STBCR7)
STBCR7 is an 8-bit readable/writable register that controls the operation of modules in power-
down modes.
Note: When writing to this register, see section 30.4, Usage Notes.
Bit: 7
6
5
4
3
2
1
0
MSTP MSTP
77 76
-
MSTP MSTP MSTP MSTP MSTP
74
73
72
71
70
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7
MSTP77 1
R/W Module Stop 77
When set to 1, the clock supply to the CMT0/CMT1 is halted.
0: CMT0/CMT1 run.
1: Clock supply to CMT0/CMT1 is halted.
6
MSTP76 1
R/W Module Stop 76
When set to 1, the clock supply to the CMT2/CMT3 is halted.
0: CMT2/CMT3 run.
1: Clock supply to CMT2/CMT3 is halted.
5

1
R
Reserved
This bit is always read as 1. The write value should always
be 1.
4
MSTP74 1
R/W Module Stop 74
When set to 1, the clock supply to the FLCTL is halted.
0: FLCTL runs.
1: Clock supply to FLCTL is halted.
3
MSTP73 1
R/W Module Stop 73
When set to 1, the clock supply to the SSU0 is halted.
0: SSU0 runs.
1: Clock supply to SSU0 is halted.
Rev. 1.00 Mar. 25, 2008 Page 1552 of 1868
REJ09B0372-0100