SH7205 Datasheet, PDF (993/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 20 Controller Area Network (RCAN-TL1)
• BCR0 (Address = H'006)
Bit: 15 14 13 12 11 10 9
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
8
7
6
5
4
3
2
1
0
-
BRP[7:0]
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W
Bits 8 to 15: Reserved. The written value should always be ‘0’ and the returned value is ‘0’.
Bits 7 to 0—Baud Rate Pre-scale (BRP[7:0] = BCR0 [7:0]): These bits are used to define the
peripheral bus clock periods contained in a Time Quantum.
Bit 7: Bit 6: Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0:
BRP[7] BRP[6] BRP[5] BRP[4] BRP[3] BRP[2] BRP[1] BRP[0] Description
0
0
0
0
0
0
0
0
2 X peripheral bus clock
(Initial value)
0
0
0
0
0
0
0
1
4 X peripheral bus clock
0
0
0
0
0
0
1
0
6 X peripheral bus clock
:
:
:
:
:
:
:
:
2*(register value + 1) X
:
:
:
:
:
:
:
:
peripheral bus clock
1
1
1
1
1
1
1
1
512 X peripheral bus clock
• Requirements of Bit Configuration Register
1-bit time (8-25 quanta)
SYNC_SEG:
SYNC_SEG
PRSEG
PHSEG1
PHSEG2
TSEG1
TSEG2
1
4-16
2-8
Quantum
Segment for establishing synchronisation of nodes on the CAN bus. (Normal bit
edge transitions occur in this segment.)
PRSEG:
Segment for compensating for physical delay between networks.
PHSEG1:
Buffer segment for correcting phase drift (positive). (This segment is extended
when synchronisation (resynchronisation) is established.)
PHSEG2:
Buffer segment for correcting phase drift (negative). (This segment is shortened
when synchronisation (resynchronisation) is established)
TSEG1:
TSG1 + 1
Rev. 1.00 Mar. 25, 2008 Page 961 of 1868
REJ09B0372-0100