SH7205 Datasheet, PDF (39/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 1 Overview
Items
Specification
Multi-function timer • Maximum 16 lines of pulse inputs/outputs based on the five channels
pulse unit 2 (MTU2)
of 16-bit timers
• 18 output-compare and input-capture registers
• Input capture function
• Pulse output modes
Toggle, PWM, complementary PWM, and reset-synchronized PWM
modes
• Synchronization of multiple counters
• Complementary PWM output mode
 Non-overlapping waveforms output for 3-phase inverter control
 Automatic dead time setting
 0% to 100% PWM duty cycle value specifiable
 A/D converter start request delaying function
 Interrupt skipping at crest or trough
• Reset-synchronized PWM mode
Three-phase PWM waveforms in positive and negative phases can be
output with a desired duty value
• Phase counting mode
Two-phase encoder pulse counting available
Compare match timer • Four channels of 16-bit counters
(CMT)
• Four types of clock can be selected (Pφ/8, Pφ/32, Pφ/128, and Pφ/512)
• DMA transfer request or interrupt request can be issued when a
compare match occurs
Watchdog timer
(WDT)
• One-channel watchdog timer × 2 cores
• A counter overflow can reset the LSI
Realtime clock (RTC) • Internal clock, calendar function, alarm function
• Interrupts can be generated at intervals of 1/256 s by the 32.768-kHz
on-chip crystal oscillator
Serial communication • Six channels
interface with FIFO
(SCIF)
• Clock synchronous or asynchronous mode selectable
• Simultaneous transmission and reception (full-duplex communication)
• Dedicated baud rate generator
• Separate 16-byte FIFO registers for transmission and reception
• Modem control function (in asynchronous mode)
Rev. 1.00 Mar. 25, 2008 Page 7 of 1868
REJ09B0372-0100