SH7205 Datasheet, PDF (1414/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
26.3.26 Panel-Output Mixing Horizontal Valid Area Setting Register for Output Block
(MGR_MIXHS)
The register MGR_MIXHS sets a valid area for signal output to the panel in the horizontal
direction. The register value is applied in synchronization with the VSYNC signal. For details, see
section 26.4.1 (5), Setting of Panel Output.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
ALLPH
Initial value: -
-
-
-
-
-
0
0
0
0
1
1
0
1
1
1
R/W: R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
VLDPH
Initial value: -
-
-
-
-
-
0
0
0
0
1
0
0
0
0
0
R/W: R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit name Value
R/W Description
31 to 26 
Undefined R
Reserved
The read value is undefined. The write value should
always be 0.
25 to 16 ALLPH
H'037
R/W Panel Output Image Horizontal Width
These bits set the horizontal width of panel output
image using the number of DCLKIN from the rising
edge of HSync_out.
Valid range: 0 to 1023 pixels
15 to 10 
Undefined R
Reserved
The read value is undefined. The write value should
always be 0.
9 to 0 VLDPH
H'020
R/W Panel Output Image Horizontal Valid Width
These bits set the valid width of panel output image
in the horizontal direction using the number of
DCLKIN from PDPH.
Valid range: 0 to 511 pixels
Note: The settings in this register and in the source E read-in area for the output block (the
MGR_SESET register) must be the same
The VLDPH bits are equivalent to the SEWIDH bits in MGR_SESET.
Rev. 1.00 Mar. 25, 2008 Page 1382 of 1868
REJ09B0372-0100