SH7205 Datasheet, PDF (1428/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
HSYNC_dck 523 524
1
2
3
4
5
6
7
8
(Internal)
VSYNC_dck
(Internal)
CSYNC
HSYNC_dck 262 263 264 265 266 267 268 269 270 271
(Internal)
VSYNC_dck
(Internal)
CSYNC
When V pulse = 3H and 1V period = 262H (2V = 524H).
VSYNC_dck rises and falls in synchronization with the falling edge of HSYNC_dck.
Figure 26.9 Timing of Internally Generated Sync Signals without VIVSYNC input (1)
(NTSC System)
HSYNC_dck
(Internal)
VSYNC_dck
(Internal)
CSYNC
621 622 623 624
1
2
3
4
5
HSYNC_dck
(Internal)
VSYNC_dck
(Internal)
CSYNC
310 311 312 313 314 315 316 317 318
When V pulse = 3H and 1V period = 312H (2V = 624H).
VSYNC_dck falls in synchronization with the falling edge of HSYNC_dck.
Figure 26.10 Timing of Internally Generated Sync Signals without VIVSYNC input (2)
(PAL System)
Rev. 1.00 Mar. 25, 2008 Page 1396 of 1868
REJ09B0372-0100