SH7205 Datasheet, PDF (1250/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value
R/W Description
3

Undefined R
Reserved
Undefined value is read from this bit. The write
value should always be 0.
2
CCPL
0
R/W Control Transfer End Enable
When the function controller function is selected,
setting this bit to 1 while the corresponding PID bits
are set to BUF allows the control transfer stages to
be completed.
Specifically, during control read transfer, this
module transmits the ACK handshake in response
to the OUT transaction from the USB host, and
outputs a zero-length packet in response to the IN
transaction from the USB host during control write
or no-data control transfer. However, on detecting
the SET_ADDRESS request, this module operates
in auto response mode from the setup stage until
completion of the status stage, irrespective of the
setting of this bit.
This bit is cleared from 1 to 0 on receiving the new
setup packet.
0: No effect
1: Completion of control transfer is enabled.
Note: While VALID is 1, writing of 1 to this bit is
disabled.
Rev. 1.00 Mar. 25, 2008 Page 1218 of 1868
REJ09B0372-0100