SH7205 Datasheet, PDF (1497/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
The 2DG handles the interrupts differently for the following two cases.
(1) When the interrupt source is a DC buffer full, an SA buffer full, an SB buffer full, or
an SE buffer full
(1-1) An interrupt event occurs in the 2DG.
(1-2) The INT_∗∗∗ and IRQ_∗∗∗ bits in the interrupt status register for graphics (GR_IRSTAT)
are set accordingly (interrupt signal = negative logic).
(1-3) The CPU recognizes the interrupt and reads the interrupt status register for graphics.
(1-4) The CPU writes 1 to the interrupt reset control register for graphics (GR_INTDIS).
(1-5) On reception of the value written in the above step, the IRQ_∗∗∗ bit in the GR_IRSTAT
register is cleared (thus deasserting the interrupt signal).
(1-6) Resetting of the response to the interrupt event proceeds within the 2DG.
(1-7) The INT_∗∗∗ bit in the GR_IRSTAT register is cleared in response to the above step.
Figure 26.57 shows the flow of processing when SB buffer full.
Note that, within the interrupt status register for graphics (GR_IRSTAT), the CPU writing a 1 to a
bit of the interrupt reset control register for graphics (in step (1-4) above) clears the bit in the case
of IRQ_∗∗∗ bits but does not clear the bit in the case of INT_∗∗∗ bits.
If an interrupt event occurs and is the response within the 2DG is cleared (step (1-6) above) before
the CPU has read the GR_ISTAT register (step (1-3) above), reading the value of the GR_ISTAT
register will return the value of the register with the corresponding INT_∗∗∗ bit cleared.
Rev. 1.00 Mar. 25, 2008 Page 1465 of 1868
REJ09B0372-0100