SH7205 Datasheet, PDF (165/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Clock Pulse Generator (CPG)
5.6.3 Note on the Resonator
Since various characteristics related to the resonator are closely linked to the user’s board design,
thorough evaluation is necessary on the user’s side, using the resonator connection examples
shown in this section as a guide. As the parameters for the oscillation circuit will depend on the
stray capacitance of the resonator and the user board, the parameters should be determined in
consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the
maximum rating is not applied to the resonator pin.
5.6.4 Note on Using a PLL Oscillation Circuit
In the PLLVcc and PLLVss connection pattern for the PLL, signal lines from the board power
supply pins must be as short as possible and pattern width must be as wide as possible to reduce
inductive interference.
In clock operating mode 2 or 3, the EXTAL pin should be pulled up and the XTAL pin left open.
Since the analog power supply for the PLL is sensitive to noise, the system may malfunction due
to interference with the other power supply. To prevent such malfunction, this analog power
supply and digital power supply for Vcc and PVcc should not be from the same resource on the
board if at all possible.
Signal lines prohibited
PLLVcc
Power supply
Vcc
PLLVss
Vss
Figure 5.5 Note on Using a PLL Oscillation Circuit
Rev. 1.00 Mar. 25, 2008 Page 133 of 1868
REJ09B0372-0100