SH7205 Datasheet, PDF (711/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Peripheral clock
(Pφ)
Counter clock
Clock
N+1
Section 13 Compare Match Timer (CMT)
CMCNT
N
0
CMCOR
N
Compare match
signal
Figure 13.4 Timing of CMF Setting
13.4.3 Timing of Compare Match Flag Clearing
The CMF bit in CMCSR is cleared by first, reading as 1 then writing to 0. However, in the case of
the DMAC being activated, the CMF bit is automatically cleared to 0 when data is transferred by
the DMAC.
Rev. 1.00 Mar. 25, 2008 Page 679 of 1868
REJ09B0372-0100