SH7205 Datasheet, PDF (1417/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
26.3.29 Graphics Block Output SYNC Position Setting Register (GR_VSDLY)
This register specifies the position of the output VSYNC signal. The vertical direction for the
moving pictures can vary with the monitor in use. In situations where this is the case, this register
can be adjusted to eliminate fluctuations in the vertical direction.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
VSDLY
Initial value: -
-
-
-
-
-
0
1
0
1
1
0
0
0
0
0
R/W: R
R
RR
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit name Value
R/W Description
31 to 10 
Undefined R
Reserved
The read value is undefined. The write value should
always be 0.
9 to 0 VSDLY
H'160
R/W Output VSYNC Position Setting
These bits adjust, in units of DCLKIN cycles, the
amount of delay to the position for output of the
VSYNC signal.
Notes: 1. When the external image is NTSC (when the NTSC bit in the MGR_MIXMODE register
has been set to 0), use the initial value (H'160). When PAL is in use, after setting this
register to H'100, set the NTSC bit in the MGR_MIXMODE register to 1.
2. Setting all bits of this register to 0 is prohibited.
Rev. 1.00 Mar. 25, 2008 Page 1385 of 1868
REJ09B0372-0100