SH7205 Datasheet, PDF (256/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 User Break Controller (UBC)
8.2 Input/Output Pin
Table 8.1 shows the pin configuration of the UBC.
Table 8.1 Pin Configuration
Pin Name
UBC trigger
Symbol
UBCTRG
I/O
Output
Function
Indicates that a setting condition is satisfied on
any one of channels 0 and 1 of UBC0 and UBC1.
8.3 Register Descriptions
The UBC has the following registers: five registers for each channel and a control register
common to channels 0 and 1. These registers are provided for each of UBC0 and UBC1.
The channel of the UBC registers is indicated as follows: for example, BAR_0 represents the BAR
register for channel 0.
Table 8.2 Register Configuration
Channel Register Name
0
Break address register_0
Break address mask register_0
Break bus cycle register_0
Break data register_0
Break data mask register_0
1
Break address register_1
Break address mask register_1
Break bus cycle register_1
Break data register_1
Break data mask register_1
Common Break control register
Abbreviation R/W
BAR_0
R/W
BAMR_0 R/W
BBR_0
R/W
BDR_0
R/W
BDMR_0 R/W
BAR_1
R/W
BAMR_1 R/W
BBR_1
R/W
BDR_1
R/W
BDMR_1 R/W
BRCR
R/W
Initial Value
H'00000000
H'00000000
H'0000
H'00000000
H'00000000
H'00000000
H'00000000
H'0000
H'00000000
H'00000000
H'00000000
Address
Access
Size
H'FFFC0400 32
H'FFFC0404 32
H'FFFC04A0 16
H'FFFC0408 32
H'FFFC040C 32
H'FFFC0410 32
H'FFFC0414 32
H'FFFC04B0 16
H'FFFC0418 32
H'FFFC041C 32
H'FFFC04C0 32
Rev. 1.00 Mar. 25, 2008 Page 224 of 1868
REJ09B0372-0100