SH7205 Datasheet, PDF (393/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
Section 11 Direct Memory Access Controller (DMAC)
The DMA controller (DMAC) is a module that handles high-speed data transfer without CPU
intervention in response to requests from software, on-chip peripheral modules, or external pins
(external modules). The DMAC itself does not distinguish between requests from on-chip
peripheral modules and those from external pins (external modules). The DMA supports data
transfer between memories, between memory and on-chip peripheral modules, and between on-
chip peripheral modules.
11.1 Features
• Number of channels: 14 channels (four channels can accept external requests; two-dimensional
addressing supported on eight channels)
• Transfer requests: Software trigger and requests from on-chip peripheral modules (48 sources)
and external pins (4 sources)
• Maximum transfer bytes: 64 Mbytes
• Address space: 4 Gbytes
• Transfer data sizes:
 Single data transfer: 8, 16, and 32 bits
 Single operand transfer: 1, 2, 4, 8, 16, 32, 64, and 128 data units
 Non-stop transfer: Until the byte counter reaches "0"
• Transfer mode:
 Cycle-stealing transfer
 Piepelined transfer
• Maximum transfer speed
 Cycle-stealing transfer: Minimum of three bus clock cycles per unit data transfer
 Pipeline transfer: Minimum of one bus clock cycle per unit data transfer
• Transfer conditions
The following transfer method can be selected.
 Unit operand transfer: Transfers data of one operand per DMA request.
Arbitrates channels per transfer of one operand.
Requires request trigger per transfer of one operand.
 Sequential operand transfer: Repeats transfer of one operand per DMA request until the
byte count reaches "0".
Arbitrates channels per transfer of one operand.
Requires only the first request trigger.
Rev. 1.00 Mar. 25, 2008 Page 361 of 1868
REJ09B0372-0100