SH7205 Datasheet, PDF (840/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 17 Synchronous Serial Communication Unit (SSU)
Initial
Bit
Bit Name Value R/W
Description
2
TIE
0
R/W
Transmit Interrupt Enable
When this bit is set to 1, generation of an SSTXI
interrupt request at transmit data empty is enabled.
1
RIE
0
R/W
Receive Interrupt Enable
When this bit is set to 1, generation of an SSRXI
interrupt request and an SSERI interrupt request upon
an overrun error are enabled.
0
CEIE
0
R/W
Conflict Error Interrupt Enable
When this bit is set to 1, generation of an SSERI
interrupt request upon a conflict error is enabled.
17.3.5 SS Status Register (SSSR)
SSSR is a status flag register for interrupts.
Bit: 7
6
5
- ORER -
Initial value: 0
0
0
R/W: R R/W R
4
3
2
1
0
- TEND TDRE RDRF CE
0
0
1
0
0
R R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W
7

0
R
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.00 Mar. 25, 2008 Page 808 of 1868
REJ09B0372-0100