SH7205 Datasheet, PDF (154/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Clock Pulse Generator (CPG)
PLL
Clock
Multiplication
Ratio of
Rate
FRQCR0 FRQCR1
Internal Clock
Operating Register Register
Frequencies Input
Mode
Setting*¹ Setting PLL Circuit (I₀:I₁:B:P)*²
Clock*³
3
H'x104 H'0000 ON (×12)
3:3:1:1/2
48
Selectable Frequency Range (MHz)
Internal Clock Internal Clock Bus Clock
Peripheral
(I₀φ)
(I₁φ)
(Bφ = CKIO Pin) Clock (Pφ)
144
144
48
24
H'x104 H'0020 ON (×12)
3:1:1:1/2
48
144
48
48
24
H'x106 H'0000 ON (×12)
3:3:1:1/4
48
144
144
48
12
H'x106 H'0020 ON (×12)
3:1:1:1/4
48
144
48
48
12
H'x124 H'0000 ON (×12)
1:3:1:1/2
48
48
144
48
24
H'x124 H'0020 ON (×12)
1:1:1:1/2
48
48
48
48
24
H'x126 H'0000 ON (×12)
1:3:1:1/4
48
48
144
48
12
H'x126 H'0020 ON (×12)
1:1:1:1/4
48
48
48
48
12
H'x205 H'0000 ON (×16)
4:4:1:1/2
48
192
192
48
24
H'x205 H'0010 ON (×16)
4:2:1:1/2
48
192
96
48
24
H'x206 H'0000 ON (×16)
4:4:1:1/4
48
192
192
48
12
H'x206 H'0010 ON (×16)
4:2:1:1/4
48
192
96
48
12
H'x215 H'0000 ON (×16)
2:4:1:1/2
48
96
192
48
24
H'x215 H'0010 ON (×16)
2:2:1:1/2
48
96
96
48
24
H'x216 H'0000 ON (×16)
2:4:1:1/4
48
96
192
48
12
H'x216 H'0010 ON (×16)
2:2:1:1/4
48
96
96
48
12
Notes: 1. x in the FRQCR0 register setting depends on the set value in bits 12, 13, and 14.
2. The ratio of clock frequencies, where the input clock frequency is assumed to be 1.
3. In mode 0 or 1, the frequency of the EXTAL pin input clock or the crystal resonator
In mode 2, the frequency of the CKIO pin input clock.
In mode 3, the frequency of the USB_X1 pin input clock or the crystal resonator
Cautions: Do not use this LSI for frequency settings other than those in table 5.3.
Rev. 1.00 Mar. 25, 2008 Page 122 of 1868
REJ09B0372-0100