SH7205 Datasheet, PDF (320/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
(a) Auto-Refresh Request Interval and DRFC Set Value
SDRAMC includes a 12-bit refresh counter that generates auto-refresh requests at fixed intervals.
The following equation is used to calculate the set value for the DRFC bits from the auto-refresh
request interval.
DRFC = (Auto-refresh request interval / System bus clock cycle) – 1
Auto-refresh requests are not accepted while SDRAM is being accessed; they must wait until the
access completes. However, the counter value is updated regardless of whether or not the request
was accepted. Note that if two or more auto-refresh requests are generated while SDRAM is being
accessed, the second and subsequent requests are ignored.
10.4.9 SDRAM Initialization Register 0 (SDIR0)
SDIR0 specifies the SDRAM initialization sequence timing.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
DPC[2:0]
DARFC[3:0]
DARFI[3:0]
Initial value: 0
0
0
0
0
-
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W
31 to 11 
All 0
R
10 to 8 DPC[2:0] Undefined R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Initialization Precharge Cycle Count Setting
These bits specify the number of precharge cycles in the
SDRAM initialization sequence.
000: 3 cycles
001: 4 cycles
:
111: 10 cycles
Rev. 1.00 Mar. 25, 2008 Page 288 of 1868
REJ09B0372-0100