SH7205 Datasheet, PDF (223/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Interrupt Controller (INTC)
(3) DREQER2
Initial
Bit Bit Name Value R/W Description
7
IIC TXI3 0
R/W DMA Transfer Enable
6
IIC RXI3 0
R/W These bits enable or disable DMA transfer requests and
5
IIC TXI2 0
R/W ^{CPU interrupt requests.}
4
IIC RXI2 0
R/W
0: DMA transfer request is disabled and CPU interrupt
request is enabled.
3
IIC TXI1 0
R/W _{1: DMA transfer request is enabled and CPU interrupt}
2
IIC RXI1 0
R/W
request is disabled.
1
IIC TXI0 0
R/W
0
IIC RXI0 0
R/W
(4) DREQER3
Bit Bit Name
7 to 4 
Initial
Value R/W
All 0 R
3
SCIF TXI5 0
R/W
2
SCIF RXI5 0
R/W
1
SCIF TXI4 0
R/W
0
SCIF RXI4 0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
DMA Transfer Enable
These bits enable or disable DMA transfer requests and
CPU interrupt requests.
0: DMA transfer request is disabled and CPU interrupt
request is enabled.
1: DMA transfer request is enabled and CPU interrupt
request is disabled.
Rev. 1.00 Mar. 25, 2008 Page 191 of 1868
REJ09B0372-0100