SH7205 Datasheet, PDF (1187/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Notes: 1. The DCP FIFO buffer should be accessed through the CFIFO port.
2. Access to the buffer memory by DMA transfer is only possible through the D0FIFO or
D1FIFO port.
3. The D1FIFO and D0FIFO ports can be accessed also by the CPU.
4. When using functions specific to the FIFO port, the pipe number (selected pipe)
specified by the CURPIPE bits cannot be changed.
5. Registers configuring a FIFO port do not affect other FIFO ports.
6. The same pipe should not be assigned to two or more FIFO ports.
7. There are two buffer memory states: the access right is on the CPU side and it is on the
SIE side. When the access right is on the SIE side, the buffer memory cannot be
accessed correctly from the CPU.
8. These registers can be accessed only while the FRDY bit in the corresponding control
register (CFIFOCTR, D0FIFOCTR, or D1FIFOCTR) is 1.
9. The valid bits in this register depend on the settings of the MBW bits (access bit width
setting) and BIGEND bit (endian setting) as shown in tables 24.9 to 24.11.
Table 24.9 Endian Operation in 32-Bit Access (when MBW = 10)
BIGEND
0
1
Bits 31 to 24
N + 3 address
N + 0 address
Bits 23 to 16
N + 2 address
N + 1 address
Bits 15 to 8
N + 1 address
N + 2 address
Bits 7 to 0
N + 0 address
N + 3 address
Table 24.10 Endian Operation in 16-Bit Access (when MBW = 01)
BIGEND
0
1
Bits 31 to 24
Bits 23 to 16
Writing: invalid, reading: prohibited
Even address
Odd address
Bits 15 to 8
Bits 7 to 0
Odd address
Even address
Writing: invalid, reading: prohibited
Table 24.11 Endian Operation in 8-Bit Access (when MBW = 00)
BIGEND
0
Bits 31 to 24
Bits 23 to 16
Writing: invalid, reading: prohibited
Bits 15 to 8
1
Writing: valid
Writing: invalid, reading: prohibited
Reading: valid
Bits 7 to 0
Writing: valid
Reading: valid
Rev. 1.00 Mar. 25, 2008 Page 1155 of 1868
REJ09B0372-0100