SH7205 Datasheet, PDF (370/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
Multiple reads
CKIO
SDRAM command
ACT RD
RD
RD
RD PRA DSL
Data bus
d0
d1
d2
d3
DRCD
(ACT-RD)
DCL
(RD-d)
DRAS
(ACT-PRA)
ACT: Row and bank activation command
RD: Read command
DSL: Deselect command
PRA: Precharge-all-banks command
DPCG
(PRA-next)
Figure 10.29 Multiple Read Timing Example 1
Multiple reads
CKIO
SDRAM command
ACT DSL RD
RD
RD
RD
PRA DSL
Data bus
d0
d1
d2
d3
DRCD
(ACT-RD)
DCL
(RD-d)
DPCG
(PRA-next)
DRAS
(ACT-PRA)
ACT: Row and bank activation command
RD: Read command
PRA: Precharge-all-banks command
DSL: Deselect command
Figure 10.30 Multiple Read Timing Example 2
Rev. 1.00 Mar. 25, 2008 Page 338 of 1868
REJ09B0372-0100