SH7205 Datasheet, PDF (725/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 14 Watchdog Timer (WDT)
14.4 WDT Usage
14.4.1 Canceling Software Standby Mode
The WDT0 can be used to cancel software standby mode with an interrupt such as an NMI
interrupt.
For details on the procedure, see section 30, Power-Down Modes.
14.4.2 Changing the PLL Multiplication Ratio
When changing the clock frequency by the PLL, use the WDT0. When changing the frequency
only by switching the divider, do not use the WDT. For details on the procedure, see section 5,
Clock Pulse Generator (CPG).
14.4.3 Using Watchdog Timer Mode
WDT0 should be used for the watchdog of CPU0 and WDT1 for the watchdog of CPU1.
1. Set the WT/IT bit in WTCSR to 1, the type of count clock in the CKS2 to CKS0 bits in
WTCSR, whether this LSI is to be reset internally or not in the RSTE bit in WRCSR, the reset
type if it is generated in the RSTS bit in WRCSR0, and the initial value of the counter in
WTCNT.
2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode.
3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent
the counter from overflowing. When the counter overflows, the WDT sets the WOVF flag in
WRCSR to 1, and the WDTOVF signal is output outside the LSI (figure 14.4). The WDTOVF
signal can be used to reset the system. The WDTOVF signal is output for 64 × Pφ clock cycles.
4. If the RSTE bit in WRCSR is set to 1, a signal to reset the inside of this LSI can be generated
simultaneously with the WDTOVF signal. Either power-on reset or manual reset can be
selected for this interrupt by the RSTS bit in WRCSR0. The internal reset signal is output for
128 × Pφ clock cycles.
5. When a WDT overflow reset is generated simultaneously with a reset input on the RES pin,
the RES pin reset takes priority, and the WOVF bit in WRCSR is cleared to 0.
Rev. 1.00 Mar. 25, 2008 Page 693 of 1868
REJ09B0372-0100