SH7205 Datasheet, PDF (645/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(2) Output Compare Output Timing
A compare match signal is generated in the final state in which TCNT and TGR match (the point
at which the count value matched by TCNT is updated). When a compare match signal is
generated, the output value set in TIOR is output at the output compare output pin (TIOC pin).
After a match between TCNT and TGR, the compare match signal is not generated until the
TCNT input clock is generated.
Figure 12.81 shows output compare output timing (normal mode and PWM mode) and figure
12.82 shows output compare output timing (complementary PWM mode and reset synchronous
PWM mode).
Pφ
TCNT input
clock
TCNT
N
N+1
TGR
N
Compare
match signal
TIOC pin
Figure 12.81 Output Compare Output Timing (Normal Mode/PWM Mode)
Rev. 1.00 Mar. 25, 2008 Page 613 of 1868
REJ09B0372-0100