SH7205 Datasheet, PDF (989/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Bit 5: GSR5
0
1
Section 20 Controller Area Network (RCAN-TL1)
Description
RCAN-TL1 is not in Error Passive or in Bus Off status (Initial value)
[Reset condition] RCAN-TL1 is in Error Active state
RCAN-TL1 is in Error Passive (if GSR0 = 0) or Bus Off (if GSR0 = 1)
[Setting condition] When TEC • 128 or REC • 128 or if Error Passive Test
Mode is selected
Bit 4 — Halt/Sleep Status Bit (GSR4): Indicates whether the CAN engine is in the halt/sleep
state or not. Please note that the clearing time of this flag is not the same as the setting time of
IRR12.
Please note that this flag reflects the status of the CAN engine and not of the full RCAN-TL1 IP.
RCAN-TL1 exits sleep mode and can be accessed once MCR5 is cleared. The CAN engine exits
sleep mode only after two additional transmission clocks on the CAN Bus.
Bit 4: GSR4
0
1
Description
RCAN-TL1 is not in the Halt state or Sleep state (Initial value)
Halt mode (if MCR1 = 1) or Sleep mode (if MCR5 = 1)
[Setting condition] If MCR1 is set and the CAN bus is either in intermission or
idle or MCR5 is set and RCAN-TL1 is in the halt mode or RCAN-TL1 is
moving to Bus Off when MCR14 and MCR6 are both set
Bit 3 — Reset Status Bit (GSR3): Indicates whether the RCAN-TL1 is in the reset state or not.
Bit 3: GSR3
0
1
Description
RCAN-TL1 is not in the reset state
Reset state (Initial value)
[Setting condition] After an RCAN-TL1 internal reset (due to SW or HW
reset)
Rev. 1.00 Mar. 25, 2008 Page 957 of 1868
REJ09B0372-0100